• Automatic Boundary Scan Test Logic Insertion
• Synthesis to technology independent IEEE 1149.1 macros
• VHDL or Verilog Input
• RT Level VHDL or Verilog Output
• Simulation Testbench in Verilog or VHDL for the Boundary Scan Circuitry
• BSDL Output for easy interface to Board Level ATE
• Custom mapping to vendor-specific JTAG cell libraries
• Custom interfaces for internal scan, memory and logic BIST

ASC's VBIT, a high-level JTAG Test Synthesis tool, frees engineers from the tedium of learning the details of IEEE 1149.1 standard and manually inserting boundary scan test logic into their ASIC, IC or MCM designs. VBIT automates the entire process.

Promotes Design Re-use

ASC was the first to introduce a JTAG Test Synthesis tool which accepts both Verilog and VHDL and automatically generates technology-independent boundary scan implementation at RT level thus promoting design re-use. Other tools lacking RT level boundary scan test insertion are used too late in the design cycle to be truly technology independent.

Furthermore, by implementing boundary scan before logic synthesis, the designers can synthesize functional core logic and test logic concurrently and avoid timing and area violations in the entire chip. This saves costly design iterations.