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Product Description

verilog2vhdl translates Verilog HDL to IEEE Standard 1076 compliant VHDL, and is the most complete Verilog HDL to VHDL translation tool available. The translator supports most synthesizable constructs (as specified in Verilog LRM, Version 2.0), as well as a large subset of unsynthesizable behavioral constructs. verilog2vhdl produces functionally equivalent VHDL compatible with any 1076 compliant VHDL simulator.

verilog2vhdl is a valuable design reuse tool because it preserves the level of abstraction during translation. There is a one-to-one mapping of constructs in most cases. Because the abstraction level is preserved, VHDL can remain technology independent in cases where the input is behavioral or RTL. verilog2vhdl output can be optimized for the ALL synthesis environments.

verilog2vhdl can:

be useful to designers working in a Verilog/VHDL environment,
be integrated into VHDL-only based tools,
provide library translation (Verilog library => VHDL library) capability, and
automate the model generation procedure.

verilog2vhdl is also available with an object-oriented Software Procedural Interface (FRITS) to access the VHDL translation of the Verilog input.

*Design Flow*

verilog2vhdl is shipping for SunOS 4.1.x, Solaris, HP-UX platforms and Windows NT.