JTAG IEEE 1149.1 continues to be a preferred method for reducing component, board, and system test costs. Increasing number of designers are implementing boundary scan test logic into their chip designs. Engineers planning to incorporate boundary scan in their designs for the first time can avoid the tedium of learning the implementation details of the IEEE 1149.1 standard by integrating ASC's VBIT automatic boundary scan test synthesis tool into their design flow.

After a chip designer has described the core logic in either VHDL or Verilog, VBIT takes that input, synthesizes the boundary scan, and outputs a new VHDL or Verilog file with test logic inserted, interconnected and wired to the core logic. The output is compliant with the IEEE 1149.1 standard. The tool also extends the JTAG standard by allowing the test access port (TAP) controller to be connected to internal test structures, such as scan, thus making the TAP controller the test manager for full-chip test.

VBIT also generates a test bench which allows automatic verification of the boundary scan circuitry at RT level. This test bench is needed for lower level tests as well. For board testing, VBIT automatically writes out a BSDL description of the synthesized boundary scan logic.

The entire process is automated and is IEEE 1149.1 compliant.

Engineers who have struggled with manually inserting or using partially

automatic tools to insert IEEE 1149.1 compliant boundary scan can cut that portion of the design time from weeks or months to a few days or hours. They will also appreciate the automatic generation of the BSDL file describing the synthesized boundary scan logic, a feature absent from many of the available tools.

Why at RT Level ?

Tools that work at the structural level insert boundary scan after logic synthesis and, sometimes, after the completion of logic and timing verification. Boundary scan insertion at this stage can violate area and timing constraints, and require additional verification steps that may add costly design iterations.

VBIT allows the designer to incorporate test logic in the earliest phase of the top-down design process. With a complete specification of test logic and core design, the synthesis and optimization process gives the designer a true picture of the chip performance.

By implementing boundary scan at RT level, the engineer can also maintain the technology independence of the design. Furthermore, the boundary scan test logic portion can be retargeted to the ASIC vendor's pre- defined JTAG library which is optimized for area and speed. This technology- specific high-level mapping, which is effectively implemented only at RT level yields better area and speed than a generic library