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verilog2vhdl (tm)

Verilog to VHDL translation

Please read the HDL Interoperability FAQ before registering for access to the verilog2vhdl documentation!

• Product Description
• The V2V Advantage
• Supported Constructs
  • Objects and Types
  • Module
  • Parameter Declaration
  • Module Instantiation
  • Gate Instantiation
  • Always Statement
  • Initial Statement
  • Conditional 'if-else-if' Statement
  • Conditional 'case' Statement
  • Conditional 'casex' and 'casez' Statement
  • Looping Statements
  • Continuous Assignments
  • Procedural Assignments
  • Non-blocking Procedural Assignment
  • Compiler Directives
  • User-defined Tasks and Functions
  • System Tasks and Functions
• Comprehensive List of (Un)supported Constructs
• Translation Examples