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What does "functionally equivalent" mean?

Functional Equivalence between Verilog and VHDL designs can be thought of as the case when Verilog and VHDL designs will produce the SAME OUTPUT for the SAME TESTS, at the SAME TIME.

VHDL simulation semantics differ considerably from Verilog simulation. verilog2vhdl ensures that the VHDL produced is functionally equivalent to input Verilog by inserting delays and simulation-specific functions where necessary.