ASC recognizes that power reduction is of utmost importance for submicron design and system on chip (SOC) architectures. Working with three government agencies and Princeton University for more than four years, ASC has developed a tool to solve the low power optimization problem.

As today's electronic designs become more complex, power consumption has increased, causing power management to become a critical design priority. Higher power consumption has a negative effect on battery life, packaging, cooling costs, and reliability. New low-power design methodologies and are necessary to address the problem.

Competition is driving the requirement for power optimization and shorter design cycles. Until now, low power design methodology has consisted of power analysis, utilizing tools that report power consumption of a design at various stages of the design cycle. This method generally results in costly design rework "spins." Today's designs require power optimization tools that address power consumption early in the design cycle and reduce time to market.

As follows from equations describing power dissipation in a circuit, there are four factors that ultimately determine the power dissipation:

• magnitude of supply voltage
• switching activity in the circuit
• switching capacitive loads
• clock frequency

Numerous optimization methods targeting each of these four factors have been explored. Reduction of supply voltage, multiple voltage supplies, reduction of capacitive loads through gate sizing, and minimization of switching activity by exploiting signal correlation are just a few. However, the four factors strongly interact in ways that may cancel out power optimization benefits obtained by adjusting only one of them. Additionally, many studies have shown that only optimizations applied sufficiently early in the design cycle, when a design's architecture is not yet fixed, have potential for radical power reduction. While gate tuning at the logic level produces reductions averaging 15%, optimizations at behavior and architectural levels can slash power consumption by close to a factor of 10. Thus, to make intelligent decisions in power optimization, the tools have to simultaneously consider all four factors affecting power dissipation, and be applied early in the design cycle.

Other factors also dictate a transition to designing at higher levels. Efficient exploration of the new delay-power-area three-dimensional space calls for new design tools with fast turnaround, and behavioral synthesis has been shown to be up to 30x faster than logic synthesis. Apart from run-time performance, designing at the behavioral level presents greater available design choices. Most importantly, the sheer complexity of today's designs forces the move to capturing designs at the behavior level, for it's hardly possible to conceptualize million-gate circuits even at the RT-level.

Figure 1. Sources of total chip power dissipation targeted by ASC's power optimization tools.

ASC is developing cutting-edge EDA solutions, which will empower the chip designers, for the first time, to optimize power simultaneously with area and speed at the early stages of the chip design. ASC's approach rests on the analysis of the multiple sources of power dissipation on a chip (Figure 1) and development of domain-specific techniques for high-level power optimization. Initial R&D and tool development was performed by ASC under several SBIR contracts from US Air Force and NASA. Princeton University is ASC's technical partner.

Product Summary

ASC's behavioral synthesis software tool is used at the beginning of the design process to dramatically reduce power consumption. It allows designs to be optimized for three parameters - power, delay, and area. The tool synthesizes behavioral HDL designs into structural RTL with the objective of minimizing power consumption. Area of the design can be treated as either a constraint, or an optimization parameter, along with power. The tool can also determine the optimal clock period for the design. The output is compatible with popular RTL synthesis tools.

A representative design flow is given in Figure 2. First, the selected RTL library is characterized, and a technology file is created. Then, synthesis of behavioral HDL design is performed. The optimized RTL HDL design can then be input to a downstream logic synthesis tool, or a compiler.

Figure 2. A high-level design flow

ASC welcomes participants in its early-access program from various segments of the industry, including semiconductors, telecommunication, computer, defense, and systems design companies, as well as universities. We invite you to participate in this breakthrough development. We also invite library vendors to characterize libraries for use with our synthesis tools.

If you have interest in evaluating the earliest release of this tool, your comments, suggestions, and feedback are welcome at information request .

R&D is partially sponsored by US Army CECOM, Fort Monmouth, NJ, NASA JPL, Pasadena, CA and Air Force Rome Laboratory, Rome, NY. The work is performed in collaboration with the Electrical Engineering Department of Princeton University.

Publications:

• K. S. Khouri, G. Lakshminarayana, and N. K. Jha, ``High-level synthesis of low power control-flow intensive circuits,'' IEEE Trans. on Computer-Aided Design, vol. 18, Dec. 1999.
• G. Lakshminarayana, A. Raghunathan, N. K. Jha, and S. Dey, ``Power management in high-level synthesis,'' IEEE Trans. on VLSI Systems, vol. 7, Mar. 1999.
• G. Lakshminarayana and N. K. Jha, ``High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors,'' IEEE Trans. on Computer-Aided Design, vol. 18, Mar. 1999.
• A. Raghunathan, S. Dey, and N. K. Jha, ``Register transfer level power optimization with emphasis on glitch analysis and reduction,'' IEEE~Trans. on Computer-Aided Design, vol. 18, Aug. 1999.
• G. Lakshminarayana and N. K. Jha, ``FACT: A framework for applying throughput and power optimizing transformations to control-flow intensive behavioral descriptions,'' IEEE Trans. on Computer-Aided Design, vol. 18, Jan. 2000