Verilog VHDL Translation software
Verilog VHDL Translation software



Next: Component Instantiations Up: Supported Constructs Previous: SignalsVariables and

Generics

VHDL GENERICS are used to construct parameterized hardware components. Verilog provides similar capabilities in the form of PARAMETERS. VHDL2verilog maps VHDL GENERICS to Verilog PARAMETERS.


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