News Release

March 2nd, 1999 - IP99 Proceedings, Santa Clara, CA, March 22-24

Abstract - The paper addresses a growing urgency within the semiconductor design industry for competent and easy translation of intellectual property (IP) from one hardware description language to another in a timely manner. Results gathered during translation of IP described at different levels (i.e. behavioral, RTL, and structural) in Verilog and VHDL are included in support of this concept. With a focus on the importance of design intent preservation, examples are presented to demonstrate how different translation starting subsets and target subsets should relate to each other in order to produce verifiable results, identical behavior, the same hardware, etc. after synthesis. The need for the translation validation phase is motivated. Common myths and misconceptions associated with translation are dispelled and the reality of each fully explained.