On the creation and licensing of innovative EDA tools for high-level design flows.
Small Business Innovation Research (SBIR) supports the development of breakthrough
methodologies that equip our customers with design products that will meet
tomorrow's challenging requirements for interoperability, testability, soft
error recovery and lowest power. |
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- HDL
Translation - VHDL2verilog™ and verilog2vhdl™
Translators are licensed and supported by partner SynaptiCAD.
- VBIT® -
IEEE Std 1149™ JTAG RTL Insertion - Preliminary support for
IEEE Std 1500 CTAG is also available.
- CoolChip™ - High-level power optimizing
design flow using PACIFIC™ and macro block library
elements such as ALF or popular design libraries.
- PACIFIC™ - ESL Power Optimizer
automatically explores the design space for best architecture
that meets timing constraint for dramatic reduction in switching
and leakage power. Removes the guesswork from low power
analysis and design.
- CORAL™ - Characterizes RTL macromodels
for power for use in ESL flows. Examples of macro-block library
components are adder, multiplier, mux, etc. CORAL supports
IEEE Std. 1603 ALF and popular industry library formats.
- OpenALF
is the open source ALF Compiler written in Perl. For
instructions on how to obtain a free copy of OpenALF,
click here. The Release 1 of OpenALF has 4 functions:
1) alf read/write, 2) .lib read/write, 3) alf to .lib
translation, and 4) .lib to alf translation.
Embeddable
Technologies
Save valuable project time by embedding proven software. Cross
license one our reusable modules (C++, XML, and Python):
- FRITS VHDL or Verilog parse tree
- IEEE Std 1603™ ALF Compiler and API
- Behavioral fault modeling
- Hardware/software co-design
- Radiation hardening by design (also for soft errors)
- VTMR™ soft error correction — Download
White Paper
Useful Information
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New Technology
Soft Error Detection and
Correction
SBIR research in radiation effects on electronic components
at ASC has spawned an innovative solution for soft errors
in logic. A university partnership technique called Virtual TMR (triple modular redundancy) detects
and corrects single bit flips on the fly. Contact ASC
for information about VTMR licensing or joint marketing
opportunities.
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